Timo Aaltonen
2018-11-09 10:22:23 UTC
Timo Aaltonen pushed to branch debian-experimental at X Strike Force / lib / mesa
Commits:
27fd1285 by Juan A. Suarez Romero at 2018-10-19T16:43:26Z
docs: add sha256 checksums for 18.2.3
Signed-off-by: Juan A. Suarez Romero <***@igalia.com>
- - - - -
8da28e56 by Alex Smith at 2018-10-22T09:21:58Z
ac/nir: Use context-specific LLVM types
LLVMInt*Type() return types from the global context and therefore are
not safe for use in other contexts. Use types from our own context
instead.
Fixes frequent crashes seen when doing multithreaded pipeline creation.
Fixes: 4d0b02bb5a "ac: add support for 16bit load_push_constant"
Fixes: 7e7ee82698 "ac: add support for 16bit buffer loads"
Cc: "18.2" <mesa-***@lists.freedesktop.org>
Signed-off-by: Alex Smith <***@feralinteractive.com>
Reviewed-by: Bas Nieuwenhuizen <***@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <***@gmail.com>
(cherry picked from commit ca83d51cfb154af12ee6e17a533df6cbbc890e22)
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8c4ff233 by Andres Rodriguez at 2018-10-22T09:26:41Z
radv: fix check for perftest options size
It was using the debug options array size.
CC: mesa-***@lists.freedesktop.org
Reviewed-by: Bas Nieuwenhuizen <***@basnieuwenhuizen.nl>
(cherry picked from commit e71a87775e48f2e26864e6c2198c7625e27bbab1)
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6899350a by Jan Vesely at 2018-10-22T09:32:37Z
radeonsi: Bump number of allowed global buffers to 32
Fixes assertion failure/crash when running luxmark/luxball on clover.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108272
CC: mesa-***@lists.freedesktop.org
Signed-off-by: Jan Vesely <***@rutgers.edu>
Reviewed-by: Marek Olšák <***@amd.com>
(cherry picked from commit 06bf56725db1827dfcb86b1d0bcd71d195fda1d2)
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c4c1c095 by Marek Olšák at 2018-10-22T09:36:25Z
radeonsi: fix a VGT hang with primitive restart on Polaris10 and later
Cc: 18.1 18.2 <mesa-***@lists.freedesktop.org>
Tested-by: Jakob Bornecrantz <***@collabora.com>
(cherry picked from commit eae8f49fc65e6e625f5e05d38c3bf1b61b84bd3d)
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f8d22f7b by Michel Dänzer at 2018-10-22T09:47:25Z
loader/dri3: Also wait for front buffer fence if we triggered it
In that case, we have to wait for the fence to synchronize with the
corresponding drawing we triggered in the X server.
Fixes incorrect display with the i965 driver and some applications, e.g.
solvespace.
Bugzilla: https://bugs.freedesktop.org/108097
Fixes: aefac10fecc9 "loader/dri3: Only wait for back buffer fences in
dri3_get_buffer"
Tested-by: Sergii Romantsov <***@globallogic.com>
(cherry picked from commit c20ba1be1843d035f36e9794bee7aea9abfc2f8b)
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e3777d9a by Connor Abbott at 2018-10-22T16:21:00Z
ac: Introduce ac_build_expand()
And implement ac_bulid_expand_to_vec4() on top of it.
Fixes: 7e7ee82698247d8f93fe37775b99f4838b0247dd ("ac: add support for 16bit buffer loads")
Reviewed-by: Marek Olšák <***@amd.com>
Reviewed-by: Bas Nieuwenhuizen <***@basnieuwenhuizen.nl>
(cherry picked from commit 59535b05cf93f7be5487bd07fb74b0d9feed24de)
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cd914013 by Connor Abbott at 2018-10-22T16:25:13Z
ac: Fix loading a dvec3 from an SSBO
The comment was wrong, since the loop above casts to a type with the
correct bitsize already.
Fixes: 7e7ee82698247d8f93fe37775b99f4838b0247dd ("ac: add support for 16bit buffer loads")
Reviewed-by: Marek Olšák <***@amd.com>
Reviewed-by: Bas Nieuwenhuizen <***@basnieuwenhuizen.nl>
(cherry picked from commit 27fe3f5b5a18c7ae404ac933dae6a9adcb2d5f7b)
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9d63cd4a by Dylan Baker at 2018-10-23T11:18:57Z
meson: don't require libelf for r600 without LLVM
r600 doesn't have a hard requirement on LLVM, and therefore doesn't have
a hard requirement on libelf. Currently the logic doesn't allow that
however.
Distro-bug: https://bugs.gentoo.org/669058
Fixes: 5060c51b6f4dfb0d5358bde6523285163d3faaad
("meson: build r600 driver")
Reviewed-by: Matt Turner <***@gmail.com>
(cherry picked from commit 4e785fb383eaa80e7def0d639eddefb781ec3f4f)
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d39924f6 by Eric Engestrom at 2018-10-23T11:29:34Z
radv: s/abs/fabsf/ for floats
Fixes: a4c4efad89eceb26cf82 "radv: Rework guard band calculation"
Signed-off-by: Eric Engestrom <***@intel.com>
Reviewed-by: Bas Nieuwenhuizen <***@basnieuwenhuizen.nl>
(cherry picked from commit 17b03b532022d4042fb2170b38dc28f5ff22bb8a)
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c13a3d4d by Liviu Prodea at 2018-10-25T08:15:45Z
scons: Put to rest zombie texture_float build option.
I found a remnant of texture_float build option that wasn't removed in
commit 66673bef941af344314fe9c91cad8cd330b245eb
This patch removes it.
Cc: mesa-***@lists.freedesktop.org
Reviewed-by: Jose Fonseca <***@vmware.com>
(cherry picked from commit d99fda17c8318af96158edc18f7532f049b4304e)
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63f01f2e by Elie Tournier at 2018-10-25T08:18:30Z
gallium: Correctly handle no config context creation
This patch fixes the following Piglit test:
***@egl_mesa_configless_context@basic
It also fixes few test in a virgl guest.
v2: Evaluate the value of no_config (Ilia)
Suggested-by: Emil Velikov <***@collabora.com>
Signed-off-by: Elie Tournier <***@collabora.com>
Signed-off-by: Marek Olšák <***@amd.com>
(cherry picked from commit 9179c745f646a85274b7a295ee3577e48f8d0d3f)
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58df8607 by Alok Hota at 2018-10-26T08:20:35Z
swr/rast: ignore CreateElementUnorderedAtomicMemCpy
This function's API changed between LLVM 5 and 6. Compile errors occur
when building with LLVM 6+ if LLVM 5 was used for a dist tarball
CC: <mesa-***@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107865
Reviewed-by: Emil Velikov <***@collabora.com>
(cherry picked from commit edf38019a070b0d2ce66160fe9ff0a94ce137539)
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a0aa50c3 by Bas Nieuwenhuizen at 2018-10-26T08:25:45Z
radv: Emit enqueued pipeline barriers on event write.
Since the CPU can read them we need to execute any GPU->CPU
flushes before the event is written.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108524
Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver"
Reviewed-by: Samuel Pitoiset <***@gmail.com>
(cherry picked from commit d41c3cc01314fd2586ad2392a05647197d04c28d)
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37ba112d by David McFarland at 2018-10-26T08:42:45Z
util: Change remaining uint32 cache ids to sha1
After discussion with Timothy Arceri. disk_cache_get_function_identifier
was using only the first byte of the sha1 build-id. Replace
disk_cache_get_function_identifier with implementation from
radv_get_build_id. Instead of writing a uint32_t it now writes to a
mesa_sha1. All drivers using disk_cache_get_function_identifier are
updated accordingly.
Reviewed-by: Timothy Arceri <***@itsqueeze.com>
Fixes: 83ea8dd99bb1 ("util: add disk_cache_get_function_identifier()")
[Juan A. Suarez: resolve trivial conflicts]
(cherry picked from commit 07a00a8729d709a4c43c828c64242c226607f09a)
Signed-off-by: Juan A. Suarez Romero <***@igalia.com>
Conflicts:
src/gallium/drivers/radeonsi/si_pipe.c
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e69b51d6 by Jason Ekstrand at 2018-10-29T09:07:33Z
spirv: Use the right bit-size for spec constant ops
Previously, we would always pull the bit size from the destination which
is wrong for opcodes like nir_ilt where the sources are variable-sized
but the destination is a fixed size. We were getting lucky before
because nir_op_ilt returns a 32-bit value and basically everyone who
uses spec constants uses 32-bit ones.
Cc: mesa-***@lists.freedesktop.org
Reviewed-by: Ian Romanick <***@intel.com>
(cherry picked from commit 8fa70cfcfdda1094bc19e9707eb9333477a2d2bf)
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14d61206 by Jason Ekstrand at 2018-10-29T09:12:53Z
blorp: Emit a dummy 3DSTATE_WM prior to 3DSTATE_WM_HZ_OP
Cc: mesa-***@lists.freedesktop.org
Suggested-by: Francisco Jerez <***@riseup.net>
Reviewed-by: Kenneth Graunke <***@whitecape.org>
(cherry picked from commit b6b2b27809b9ce1cb8fdeb63fb4244c8a584434e)
[Juan A. Suarez: resolve trivial conflicts]
Signed-off-by: Juan A. Suarez Romero <***@igalia.com>
Conflicts:
src/intel/blorp/blorp_genX_exec.h
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957c148a by Juan A. Suarez Romero at 2018-10-29T09:54:41Z
cherry-ignore: Revert "anv/skylake: disable ForceThreadDispatchEnable"
pick: This commit reverts 0fa9e6d7b30 which did not land in branch.
Signed-off-by: Juan A. Suarez Romero <***@igalia.com>
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8afef6d5 by Alex Smith at 2018-10-29T09:58:09Z
anv: Fix sanitization of stencil state when the depth test is disabled
When depth testing is disabled, we shouldn't pay attention to the
specified depthCompareOp, and just treat it as always passing. Before,
if the depth test is disabled, but depthCompareOp is VK_COMPARE_OP_NEVER
(e.g. from the app having zero-initialized the structure), then
sanitize_stencil_face() would have incorrectly changed passOp to
VK_STENCIL_OP_KEEP.
v2: Roll the depthTestEnable check into the ds_aspect check below since
they now both do the same thing.
Fixes: 028e1137e6 "anv/pipeline: Be smarter about depth/stencil state"
Signed-off-by: Alex Smith <***@feralinteractive.com>
Reviewed-by: Jason Ekstrand <***@jlekstrand.net>
(cherry picked from commit 3bd239f71dc9365025c879c3a658493a6ca3504f)
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aaff8c7a by Nanley Chery at 2018-10-29T10:02:58Z
intel/blorp: Define the clear value bounds for HiZ clears
Follow the restriction of making sure the clear value is between the min
and max values defined in CC_VIEWPORT. Avoids a simulator warning for
some piglit tests, one of them being:
./bin/depthstencil-render-miplevels 146 d=z32f_s8
Jason found this to fix incorrect clearing on SKL.
Fixes: 09948151ab1d5184b4dd9052bb1f710fa1e00a7b
("intel/blorp: Add the BDW+ optimized HZ_OP sequence to BLORP")
Reviewed-by: Jason Ekstrand <***@jlekstrand.net>
Tested-by: Jason Ekstrand <***@jlekstrand.net>
(cherry picked from commit 5bcf479524b96554cab7d2429dacf650b4054638)
[Juan A. Suarez: resolve trivial conflicts]
Signed-off-by: Juan A. Suarez Romero <***@igalia.com>
Conflicts:
src/intel/blorp/blorp_genX_exec.h
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2edd62b4 by Jason Ekstrand at 2018-10-29T10:13:22Z
anv: Flag semaphore BOs as external
It probably doesn't actually break anything but it does cause some
assertions in debug builds.
Fixes: 7a89a0d9edae6 "anv: Use separate MOCS settings for external BOs"
Reviewed-by: Lionel Landwerlin <***@intel.com>
(cherry picked from commit cbd44686952b4275d654bcb3555111b412b8c8f4)
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b8ddd70d by Rob Clark at 2018-10-29T10:25:48Z
freedreno: fix inorder rendering case
Signed-off-by: Rob Clark <***@gmail.com>
(cherry picked from commit 12de415ad1abb67863f6efb7394552a12b9e3b4b)
[Juan A. Suarez: resolve trivial conflicts]
Signed-off-by: Juan A. Suarez Romero <***@igalia.com>
Conflicts:
src/gallium/drivers/freedreno/freedreno_state.c
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c4bb9bc0 by Rob Clark at 2018-10-29T10:26:19Z
freedreno: don't flush when new and old pfb is identical
In the 'inorder' case (ie. FD_MESA_DEBUG=inorder, or old kernel), if the
u_blitter clear path is used (a3xx, a4xx, and some fallback cases on
newer gens), util_blitter_restore_fb_state() will set_framebuffer_state()
to something that is identical to the current fb state, which triggers
an unnecessary flush, and then eventually an assert:
(gdb) bt
#0 0x0000007fbf24a078 in kill () from /lib64/libc.so.6
#1 0x0000007fbe061278 in _debug_assert_fail (expr=0x7fbe93a820 "!batch->flushed", file=0x7fbe93a628 "../src/gallium/drivers/freedreno/freedreno_batch.c", line=491, function=0x7fbe93a990 <__func__.17380> "fd_batch_check_size") at ../src/gallium/auxiliary/util/u_debug.c:322
#2 0x0000007fbe1ccb8c in fd_batch_check_size (batch=0x55556d5a70) at ../src/gallium/drivers/freedreno/freedreno_batch.c:491
#3 0x0000007fbe1d0e08 in fd_clear (pctx=0x55555c61e0, buffers=5, color=0x55556e388c, depth=1, stencil=0) at ../src/gallium/drivers/freedreno/freedreno_draw.c:463
#4 0x0000007fbe57afa4 in st_Clear (ctx=0x55556e17b0, mask=18) at ../src/mesa/state_tracker/st_cb_clear.c:452
The assert was introduced in 4b847b38ae3, so from a functionality
standpoint this patch fixes that commit. But it should also avoid an
unnecessary flush in the 'inorder' case, fixing a performance bug.
Fixes: 4b847b38ae3 freedreno: make fd_batch a one-shot thing
Signed-off-by: Rob Clark <***@gmail.com>
(cherry picked from commit a61952e7374c3d30cf05765245bf6f5d5fcbe900)
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b5ecce3c by Alok Hota at 2018-10-29T10:35:13Z
swr/rast: fix intrinsic/function for LLVM 7 compatibility
Converted from x86 VFMADDPS intrinsic to generic LLVM intrinsic, and
removed createInstructionSimplifierPass, which were both removed in LLVM
7.0.0
These changes combine patches we received from the community and our own
internal patches
Reviewed-by: Bruce Cherniak <***@intel.com>
Tested-by: Chuck Atkins <***@kitware.com>
(cherry picked from commit 8c872ac2e39affb2df3586a596e44a029535949d)
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7e0f6667 by Juan A. Suarez Romero at 2018-10-31T18:01:02Z
Update version to 18.2.4
Signed-off-by: Juan A. Suarez Romero <***@igalia.com>
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1cdef5e7 by Juan A. Suarez Romero at 2018-10-31T18:04:16Z
docs: add release notes for 18.2.4
Signed-off-by: Juan A. Suarez Romero <***@igalia.com>
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40167f93 by Timo Aaltonen at 2018-11-07T12:26:01Z
Merge branch 'upstream-experimental' into debian-experimental
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391b6469 by Timo Aaltonen at 2018-11-07T12:29:50Z
bump the version
- - - - -
30 changed files:
- VERSION
- bin/.cherry-ignore
- common.py
- debian/changelog
- docs/relnotes/18.2.3.html
- + docs/relnotes/18.2.4.html
- meson.build
- src/amd/common/ac_llvm_build.c
- src/amd/common/ac_llvm_build.h
- src/amd/common/ac_nir_to_llvm.c
- src/amd/vulkan/radv_cmd_buffer.c
- src/amd/vulkan/radv_device.c
- src/amd/vulkan/si_cmd_buffer.c
- src/compiler/spirv/spirv_to_nir.c
- src/gallium/drivers/freedreno/freedreno_state.c
- src/gallium/drivers/nouveau/nouveau_screen.c
- src/gallium/drivers/r600/r600_pipe_common.c
- src/gallium/drivers/radeonsi/si_compute.h
- src/gallium/drivers/radeonsi/si_pipe.c
- src/gallium/drivers/radeonsi/si_state_draw.c
- src/gallium/drivers/swr/rasterizer/codegen/gen_llvm_ir_macros.py
- src/gallium/drivers/swr/rasterizer/jitter/blend_jit.cpp
- src/gallium/drivers/swr/rasterizer/jitter/builder_misc.cpp
- src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp
- src/gallium/drivers/swr/rasterizer/jitter/functionpasses/lower_x86.cpp
- src/gallium/drivers/swr/rasterizer/jitter/streamout_jit.cpp
- src/gallium/include/state_tracker/st_api.h
- src/gallium/state_trackers/dri/dri_screen.c
- src/intel/blorp/blorp_genX_exec.h
- src/intel/vulkan/anv_queue.c
The diff was not included because it is too large.
View it on GitLab: https://salsa.debian.org/xorg-team/lib/mesa/compare/16a3623517ca06559a894fa3ce865d66bdaa8e70...391b64698b0e60a6d17dc52c0c02186d00e7549e
Commits:
27fd1285 by Juan A. Suarez Romero at 2018-10-19T16:43:26Z
docs: add sha256 checksums for 18.2.3
Signed-off-by: Juan A. Suarez Romero <***@igalia.com>
- - - - -
8da28e56 by Alex Smith at 2018-10-22T09:21:58Z
ac/nir: Use context-specific LLVM types
LLVMInt*Type() return types from the global context and therefore are
not safe for use in other contexts. Use types from our own context
instead.
Fixes frequent crashes seen when doing multithreaded pipeline creation.
Fixes: 4d0b02bb5a "ac: add support for 16bit load_push_constant"
Fixes: 7e7ee82698 "ac: add support for 16bit buffer loads"
Cc: "18.2" <mesa-***@lists.freedesktop.org>
Signed-off-by: Alex Smith <***@feralinteractive.com>
Reviewed-by: Bas Nieuwenhuizen <***@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <***@gmail.com>
(cherry picked from commit ca83d51cfb154af12ee6e17a533df6cbbc890e22)
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8c4ff233 by Andres Rodriguez at 2018-10-22T09:26:41Z
radv: fix check for perftest options size
It was using the debug options array size.
CC: mesa-***@lists.freedesktop.org
Reviewed-by: Bas Nieuwenhuizen <***@basnieuwenhuizen.nl>
(cherry picked from commit e71a87775e48f2e26864e6c2198c7625e27bbab1)
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6899350a by Jan Vesely at 2018-10-22T09:32:37Z
radeonsi: Bump number of allowed global buffers to 32
Fixes assertion failure/crash when running luxmark/luxball on clover.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108272
CC: mesa-***@lists.freedesktop.org
Signed-off-by: Jan Vesely <***@rutgers.edu>
Reviewed-by: Marek Olšák <***@amd.com>
(cherry picked from commit 06bf56725db1827dfcb86b1d0bcd71d195fda1d2)
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c4c1c095 by Marek Olšák at 2018-10-22T09:36:25Z
radeonsi: fix a VGT hang with primitive restart on Polaris10 and later
Cc: 18.1 18.2 <mesa-***@lists.freedesktop.org>
Tested-by: Jakob Bornecrantz <***@collabora.com>
(cherry picked from commit eae8f49fc65e6e625f5e05d38c3bf1b61b84bd3d)
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f8d22f7b by Michel Dänzer at 2018-10-22T09:47:25Z
loader/dri3: Also wait for front buffer fence if we triggered it
In that case, we have to wait for the fence to synchronize with the
corresponding drawing we triggered in the X server.
Fixes incorrect display with the i965 driver and some applications, e.g.
solvespace.
Bugzilla: https://bugs.freedesktop.org/108097
Fixes: aefac10fecc9 "loader/dri3: Only wait for back buffer fences in
dri3_get_buffer"
Tested-by: Sergii Romantsov <***@globallogic.com>
(cherry picked from commit c20ba1be1843d035f36e9794bee7aea9abfc2f8b)
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e3777d9a by Connor Abbott at 2018-10-22T16:21:00Z
ac: Introduce ac_build_expand()
And implement ac_bulid_expand_to_vec4() on top of it.
Fixes: 7e7ee82698247d8f93fe37775b99f4838b0247dd ("ac: add support for 16bit buffer loads")
Reviewed-by: Marek Olšák <***@amd.com>
Reviewed-by: Bas Nieuwenhuizen <***@basnieuwenhuizen.nl>
(cherry picked from commit 59535b05cf93f7be5487bd07fb74b0d9feed24de)
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cd914013 by Connor Abbott at 2018-10-22T16:25:13Z
ac: Fix loading a dvec3 from an SSBO
The comment was wrong, since the loop above casts to a type with the
correct bitsize already.
Fixes: 7e7ee82698247d8f93fe37775b99f4838b0247dd ("ac: add support for 16bit buffer loads")
Reviewed-by: Marek Olšák <***@amd.com>
Reviewed-by: Bas Nieuwenhuizen <***@basnieuwenhuizen.nl>
(cherry picked from commit 27fe3f5b5a18c7ae404ac933dae6a9adcb2d5f7b)
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9d63cd4a by Dylan Baker at 2018-10-23T11:18:57Z
meson: don't require libelf for r600 without LLVM
r600 doesn't have a hard requirement on LLVM, and therefore doesn't have
a hard requirement on libelf. Currently the logic doesn't allow that
however.
Distro-bug: https://bugs.gentoo.org/669058
Fixes: 5060c51b6f4dfb0d5358bde6523285163d3faaad
("meson: build r600 driver")
Reviewed-by: Matt Turner <***@gmail.com>
(cherry picked from commit 4e785fb383eaa80e7def0d639eddefb781ec3f4f)
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d39924f6 by Eric Engestrom at 2018-10-23T11:29:34Z
radv: s/abs/fabsf/ for floats
Fixes: a4c4efad89eceb26cf82 "radv: Rework guard band calculation"
Signed-off-by: Eric Engestrom <***@intel.com>
Reviewed-by: Bas Nieuwenhuizen <***@basnieuwenhuizen.nl>
(cherry picked from commit 17b03b532022d4042fb2170b38dc28f5ff22bb8a)
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c13a3d4d by Liviu Prodea at 2018-10-25T08:15:45Z
scons: Put to rest zombie texture_float build option.
I found a remnant of texture_float build option that wasn't removed in
commit 66673bef941af344314fe9c91cad8cd330b245eb
This patch removes it.
Cc: mesa-***@lists.freedesktop.org
Reviewed-by: Jose Fonseca <***@vmware.com>
(cherry picked from commit d99fda17c8318af96158edc18f7532f049b4304e)
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63f01f2e by Elie Tournier at 2018-10-25T08:18:30Z
gallium: Correctly handle no config context creation
This patch fixes the following Piglit test:
***@egl_mesa_configless_context@basic
It also fixes few test in a virgl guest.
v2: Evaluate the value of no_config (Ilia)
Suggested-by: Emil Velikov <***@collabora.com>
Signed-off-by: Elie Tournier <***@collabora.com>
Signed-off-by: Marek Olšák <***@amd.com>
(cherry picked from commit 9179c745f646a85274b7a295ee3577e48f8d0d3f)
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58df8607 by Alok Hota at 2018-10-26T08:20:35Z
swr/rast: ignore CreateElementUnorderedAtomicMemCpy
This function's API changed between LLVM 5 and 6. Compile errors occur
when building with LLVM 6+ if LLVM 5 was used for a dist tarball
CC: <mesa-***@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107865
Reviewed-by: Emil Velikov <***@collabora.com>
(cherry picked from commit edf38019a070b0d2ce66160fe9ff0a94ce137539)
- - - - -
a0aa50c3 by Bas Nieuwenhuizen at 2018-10-26T08:25:45Z
radv: Emit enqueued pipeline barriers on event write.
Since the CPU can read them we need to execute any GPU->CPU
flushes before the event is written.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108524
Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver"
Reviewed-by: Samuel Pitoiset <***@gmail.com>
(cherry picked from commit d41c3cc01314fd2586ad2392a05647197d04c28d)
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37ba112d by David McFarland at 2018-10-26T08:42:45Z
util: Change remaining uint32 cache ids to sha1
After discussion with Timothy Arceri. disk_cache_get_function_identifier
was using only the first byte of the sha1 build-id. Replace
disk_cache_get_function_identifier with implementation from
radv_get_build_id. Instead of writing a uint32_t it now writes to a
mesa_sha1. All drivers using disk_cache_get_function_identifier are
updated accordingly.
Reviewed-by: Timothy Arceri <***@itsqueeze.com>
Fixes: 83ea8dd99bb1 ("util: add disk_cache_get_function_identifier()")
[Juan A. Suarez: resolve trivial conflicts]
(cherry picked from commit 07a00a8729d709a4c43c828c64242c226607f09a)
Signed-off-by: Juan A. Suarez Romero <***@igalia.com>
Conflicts:
src/gallium/drivers/radeonsi/si_pipe.c
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e69b51d6 by Jason Ekstrand at 2018-10-29T09:07:33Z
spirv: Use the right bit-size for spec constant ops
Previously, we would always pull the bit size from the destination which
is wrong for opcodes like nir_ilt where the sources are variable-sized
but the destination is a fixed size. We were getting lucky before
because nir_op_ilt returns a 32-bit value and basically everyone who
uses spec constants uses 32-bit ones.
Cc: mesa-***@lists.freedesktop.org
Reviewed-by: Ian Romanick <***@intel.com>
(cherry picked from commit 8fa70cfcfdda1094bc19e9707eb9333477a2d2bf)
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14d61206 by Jason Ekstrand at 2018-10-29T09:12:53Z
blorp: Emit a dummy 3DSTATE_WM prior to 3DSTATE_WM_HZ_OP
Cc: mesa-***@lists.freedesktop.org
Suggested-by: Francisco Jerez <***@riseup.net>
Reviewed-by: Kenneth Graunke <***@whitecape.org>
(cherry picked from commit b6b2b27809b9ce1cb8fdeb63fb4244c8a584434e)
[Juan A. Suarez: resolve trivial conflicts]
Signed-off-by: Juan A. Suarez Romero <***@igalia.com>
Conflicts:
src/intel/blorp/blorp_genX_exec.h
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957c148a by Juan A. Suarez Romero at 2018-10-29T09:54:41Z
cherry-ignore: Revert "anv/skylake: disable ForceThreadDispatchEnable"
pick: This commit reverts 0fa9e6d7b30 which did not land in branch.
Signed-off-by: Juan A. Suarez Romero <***@igalia.com>
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8afef6d5 by Alex Smith at 2018-10-29T09:58:09Z
anv: Fix sanitization of stencil state when the depth test is disabled
When depth testing is disabled, we shouldn't pay attention to the
specified depthCompareOp, and just treat it as always passing. Before,
if the depth test is disabled, but depthCompareOp is VK_COMPARE_OP_NEVER
(e.g. from the app having zero-initialized the structure), then
sanitize_stencil_face() would have incorrectly changed passOp to
VK_STENCIL_OP_KEEP.
v2: Roll the depthTestEnable check into the ds_aspect check below since
they now both do the same thing.
Fixes: 028e1137e6 "anv/pipeline: Be smarter about depth/stencil state"
Signed-off-by: Alex Smith <***@feralinteractive.com>
Reviewed-by: Jason Ekstrand <***@jlekstrand.net>
(cherry picked from commit 3bd239f71dc9365025c879c3a658493a6ca3504f)
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aaff8c7a by Nanley Chery at 2018-10-29T10:02:58Z
intel/blorp: Define the clear value bounds for HiZ clears
Follow the restriction of making sure the clear value is between the min
and max values defined in CC_VIEWPORT. Avoids a simulator warning for
some piglit tests, one of them being:
./bin/depthstencil-render-miplevels 146 d=z32f_s8
Jason found this to fix incorrect clearing on SKL.
Fixes: 09948151ab1d5184b4dd9052bb1f710fa1e00a7b
("intel/blorp: Add the BDW+ optimized HZ_OP sequence to BLORP")
Reviewed-by: Jason Ekstrand <***@jlekstrand.net>
Tested-by: Jason Ekstrand <***@jlekstrand.net>
(cherry picked from commit 5bcf479524b96554cab7d2429dacf650b4054638)
[Juan A. Suarez: resolve trivial conflicts]
Signed-off-by: Juan A. Suarez Romero <***@igalia.com>
Conflicts:
src/intel/blorp/blorp_genX_exec.h
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2edd62b4 by Jason Ekstrand at 2018-10-29T10:13:22Z
anv: Flag semaphore BOs as external
It probably doesn't actually break anything but it does cause some
assertions in debug builds.
Fixes: 7a89a0d9edae6 "anv: Use separate MOCS settings for external BOs"
Reviewed-by: Lionel Landwerlin <***@intel.com>
(cherry picked from commit cbd44686952b4275d654bcb3555111b412b8c8f4)
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b8ddd70d by Rob Clark at 2018-10-29T10:25:48Z
freedreno: fix inorder rendering case
Signed-off-by: Rob Clark <***@gmail.com>
(cherry picked from commit 12de415ad1abb67863f6efb7394552a12b9e3b4b)
[Juan A. Suarez: resolve trivial conflicts]
Signed-off-by: Juan A. Suarez Romero <***@igalia.com>
Conflicts:
src/gallium/drivers/freedreno/freedreno_state.c
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c4bb9bc0 by Rob Clark at 2018-10-29T10:26:19Z
freedreno: don't flush when new and old pfb is identical
In the 'inorder' case (ie. FD_MESA_DEBUG=inorder, or old kernel), if the
u_blitter clear path is used (a3xx, a4xx, and some fallback cases on
newer gens), util_blitter_restore_fb_state() will set_framebuffer_state()
to something that is identical to the current fb state, which triggers
an unnecessary flush, and then eventually an assert:
(gdb) bt
#0 0x0000007fbf24a078 in kill () from /lib64/libc.so.6
#1 0x0000007fbe061278 in _debug_assert_fail (expr=0x7fbe93a820 "!batch->flushed", file=0x7fbe93a628 "../src/gallium/drivers/freedreno/freedreno_batch.c", line=491, function=0x7fbe93a990 <__func__.17380> "fd_batch_check_size") at ../src/gallium/auxiliary/util/u_debug.c:322
#2 0x0000007fbe1ccb8c in fd_batch_check_size (batch=0x55556d5a70) at ../src/gallium/drivers/freedreno/freedreno_batch.c:491
#3 0x0000007fbe1d0e08 in fd_clear (pctx=0x55555c61e0, buffers=5, color=0x55556e388c, depth=1, stencil=0) at ../src/gallium/drivers/freedreno/freedreno_draw.c:463
#4 0x0000007fbe57afa4 in st_Clear (ctx=0x55556e17b0, mask=18) at ../src/mesa/state_tracker/st_cb_clear.c:452
The assert was introduced in 4b847b38ae3, so from a functionality
standpoint this patch fixes that commit. But it should also avoid an
unnecessary flush in the 'inorder' case, fixing a performance bug.
Fixes: 4b847b38ae3 freedreno: make fd_batch a one-shot thing
Signed-off-by: Rob Clark <***@gmail.com>
(cherry picked from commit a61952e7374c3d30cf05765245bf6f5d5fcbe900)
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b5ecce3c by Alok Hota at 2018-10-29T10:35:13Z
swr/rast: fix intrinsic/function for LLVM 7 compatibility
Converted from x86 VFMADDPS intrinsic to generic LLVM intrinsic, and
removed createInstructionSimplifierPass, which were both removed in LLVM
7.0.0
These changes combine patches we received from the community and our own
internal patches
Reviewed-by: Bruce Cherniak <***@intel.com>
Tested-by: Chuck Atkins <***@kitware.com>
(cherry picked from commit 8c872ac2e39affb2df3586a596e44a029535949d)
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7e0f6667 by Juan A. Suarez Romero at 2018-10-31T18:01:02Z
Update version to 18.2.4
Signed-off-by: Juan A. Suarez Romero <***@igalia.com>
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1cdef5e7 by Juan A. Suarez Romero at 2018-10-31T18:04:16Z
docs: add release notes for 18.2.4
Signed-off-by: Juan A. Suarez Romero <***@igalia.com>
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40167f93 by Timo Aaltonen at 2018-11-07T12:26:01Z
Merge branch 'upstream-experimental' into debian-experimental
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391b6469 by Timo Aaltonen at 2018-11-07T12:29:50Z
bump the version
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30 changed files:
- VERSION
- bin/.cherry-ignore
- common.py
- debian/changelog
- docs/relnotes/18.2.3.html
- + docs/relnotes/18.2.4.html
- meson.build
- src/amd/common/ac_llvm_build.c
- src/amd/common/ac_llvm_build.h
- src/amd/common/ac_nir_to_llvm.c
- src/amd/vulkan/radv_cmd_buffer.c
- src/amd/vulkan/radv_device.c
- src/amd/vulkan/si_cmd_buffer.c
- src/compiler/spirv/spirv_to_nir.c
- src/gallium/drivers/freedreno/freedreno_state.c
- src/gallium/drivers/nouveau/nouveau_screen.c
- src/gallium/drivers/r600/r600_pipe_common.c
- src/gallium/drivers/radeonsi/si_compute.h
- src/gallium/drivers/radeonsi/si_pipe.c
- src/gallium/drivers/radeonsi/si_state_draw.c
- src/gallium/drivers/swr/rasterizer/codegen/gen_llvm_ir_macros.py
- src/gallium/drivers/swr/rasterizer/jitter/blend_jit.cpp
- src/gallium/drivers/swr/rasterizer/jitter/builder_misc.cpp
- src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp
- src/gallium/drivers/swr/rasterizer/jitter/functionpasses/lower_x86.cpp
- src/gallium/drivers/swr/rasterizer/jitter/streamout_jit.cpp
- src/gallium/include/state_tracker/st_api.h
- src/gallium/state_trackers/dri/dri_screen.c
- src/intel/blorp/blorp_genX_exec.h
- src/intel/vulkan/anv_queue.c
The diff was not included because it is too large.
View it on GitLab: https://salsa.debian.org/xorg-team/lib/mesa/compare/16a3623517ca06559a894fa3ce865d66bdaa8e70...391b64698b0e60a6d17dc52c0c02186d00e7549e
--
View it on GitLab: https://salsa.debian.org/xorg-team/lib/mesa/compare/16a3623517ca06559a894fa3ce865d66bdaa8e70...391b64698b0e60a6d17dc52c0c02186d00e7549e
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